In recent years, employment of SiC (silicon carbide) has been discussed as the next-generation power device material implementing a high withstand voltage and low on-resistance.
Further, a trench gate structure is known as a structure for refinement of the power device and reduction of the on-resistance. For example, a power MOSFET employing the trench gate structure increasingly forms the mainstream.
FIG. 12 is a schematic sectional view of a conventional SiC semiconductor device having a trench gate VDMOSFET.
A semiconductor device 101 includes an N+-type SiC substrate 102 forming the base of the semiconductor device 101. An N−-type epitaxial layer 103 made of SiC (silicon carbide) doped with an N-type impurity in a lower concentration than the SiC substrate 102 is stacked on an Si plane (a silicon plane) of the SiC substrate 102. A base layer portion of the epitaxial layer 103 forms an N−-type drain region 104 maintaining a state after epitaxy. In the epitaxial layer 103, a P-type body region 105 is formed on the drain region 104 in contact with the drain region 104.
A gate trench 106 is formed in the epitaxial layer 103 to be dug down from a surface 117 (an Si plane) thereof. The gate trench 106 passes through the body region 105 in the thickness direction, and the deepest portion (a bottom surface 116) thereof reaches the drain region 104.
In the gate trench 106, a gate insulating film 107 made of SiO2 is formed on the whole areas of the inner surfaces of the gate trench 106, by thermally oxidizing side surfaces 114 and the bottom surface 116 of the gate trench 106.
A gate electrode 108 is embedded in the gate trench 106 by filling up the inner side of the gate insulating film 107 with polysilicon doped with an N-type impurity in a high concentration.
On a surface layer portion of the epitaxial layer 103, N+-type source regions 109 are formed on both sides of the gate trench 106 in a direction (the right-and-left direction in FIG. 12) orthogonal to the gate width. The source regions 109 extend along the gate trench 106 in a direction along the gate width, and the bottom portions thereof are in contact with the body region 105.
In the epitaxial layer 103, P+-type body contact regions 110 passing through central portions of the source regions 109 in the direction orthogonal to the gate width to be connected to the body region 105 are formed from the surface 117 thereof.
An interlayer dielectric film 111 made of SiO2 is stacked on the epitaxial layer 103. A source wire 112 is formed on the interlayer dielectric film 111. The source wire 112 is grounded. The source wire 112 is electrically connected to the source regions 109 and the body contact regions 110 through contact holes 113 formed in the interlayer dielectric film 111.
A drain wire 115 is formed on the back surface (a carbon plane: C plane) of the SiC substrate 102.
A prescribed voltage (a voltage exceeding a gate threshold voltage) is applied to the gate electrode 108 in a state causing a prescribed potential difference between the source wire 112 and the drain wire 115 (between a source and a drain), whereby a channel is formed in the vicinity of the interface between the body region 105 and the gate insulating film 107 by an electric field from the gate electrode 108. Thus, a current flows between the source wire 112 and the drain wire 115, and the VDMOSFET enters an ON state.